1. Field of the Invention
The invention in general relates to the fabrication of layered superlattice materials and ABO.sub.3 type metal oxides, and more particularly to fabrication processes that provide high-polarizability and low fatigue ferroelectric integrated circuit devices and low-leakage current high dielectric constant integrated circuit devices without exposure to oxygen at high temperatures.
2. Statement of the Problem
It has been known for more than 30 years that if a memory utilizing the polarizability property of ferroelectric materials could be made, such a memory would be non-volatile, of high density, and have many other advantages. See, for example, U.S. Pat. No. 5,046,043 issued to William D. Miller et al. It is also known that the substitution of high dielectric constant materials for the silicon dioxide of conventional memories such as DRAM's could result in memories that were much more dense. See, for example, European Patent Application Serial No. 0 415 751 A1 of NEC Corporation. Thus, a large amount of research has been performed for many years to obtain materials with suitable ferroelectric properties and suitable high dielectric constant properties. However, until recently, no one had been able to find a material that had ferroelectric properties or high dielectric properties that made it suitable for fabricating a practical ferroelectric memory or dielectric memory with a suitably high dielectric constant. All ferroelectric materials with suitably high polarizabilities fatigued, and most dielectric materials with suitably high dielectric constant had excessive leakage currents.
U.S. Pat. No. 5,519,234 issued May 21, 1996 discloses that layered superlattice materials, such as strontium bismuth tantalate, have excellent properties in ferroelectric applications as compared to the best prior materials and have high dielectric constants and low leakage currents. U.S. Pat. Nos. 5,434,102 issued Jul. 18, 1995 and 5,468,684 issued Nov. 21, 1995 describe processes for integrating these materials into practical integrated circuits. U.S. Pat. No. 5,508,226 issued Apr. 16, 1996 discloses a process for making layered superlattice materials in which a lower temperature anneal of about 700.degree. C. is used.
The processes for fabricating layered superlattice materials described in the above patents and all other prior art all include high temperature oxygen anneals, i.e. anneals in oxygen at temperatures higher than 600.degree. C. According to all the prior art relating to the fabrication of layered superlattice materials, high temperature anneals in oxygen are required to produce a high polarizability and other electronic properties which are necessary for use of these materials in integrated circuits. See, for example, U.S. Pat. No. 5,508,226. According to the prior art, this is because the layered superlattice materials utilized in these patents are all complex oxides and the oxygen is required to assure that oxygen vacancy defects are not created in the fabrication process.
While fabricating processes using high temperature anneals in oxygen do produce layered superlattice materials with excellent electrical properties for use in integrated circuits, they also have significant deleterious effects on many conventional integrated circuit materials. For example, materials such as polysilicon and titanium that are commonly used as conductors in integrated circuits oxidize in such anneals and become insulators. This creates thin capacitors in areas where they are not desirable. Exposure to oxygen at high temperatures can also lead to defects in many materials used in integrated circuits, such as semiconducting silicon.
The prior art has attempted to avoid these destructive effects of high temperature oxygen anneals by device designs which isolate the layered superlattice materials from the transistors and other sensitive conventional integrated circuit components. For example, U.S. Pat. No. 5,468,684 issued Nov. 21, 1995 locates the layered superlattice material capacitors on a thick protective coating well above and away from the transistor. This however, results in an integrated circuit that is less dense than it would otherwise be. Other prior art has used barrier layers to attempt to avoid damaging the sensitive integrated circuit components, but the barrier layers are also susceptible to damage by the high temperature oxygen anneals. Thus, it would be highly desirable to have a layered superlattice material fabrication process that produces high quality electronic devices without using a high temperature oxygen anneal.